2021.07.24 13:00 UTC



Loongson’s first LoongArch processors – 3A5000 for computers, 3C5000L for servers

2021-07-24 06:37 CNXSoft Jean-Luc Aufranc (CNXSoft)

Loongson has officially launched the first processors based on LoongArch CPU instruction set architecture designed...


OSS+ELC show returns live with RISC-V, AI, Martian rovers, and 30 years of Tux

2021-07-23 22:55 LinuxGizmos Eric Brown

The Linux Foundation has posted a schedule for its Open Source Summit + Embedded Linux Conference, to be held (live this time) on Sep. 27 to Oct. 1 in Seattle. RISC-V is a big topic, and there is a keynote on the Martian Perseverance rover and Ingenuity helicopter. The Open Source Summit + Embedded Linux […]


UK made: Sacrificial anodes for wind farms

2021-07-23 15:48 ElectronicsWeekly Steve Bush

South Tyneside sacrificial anode manufacture Metec UK has signed contracts worth over £6.5m, to supply Dogger Bank Wind Farm phases A and B, and an off-shore substation in France. “We’re delighted to win these latest contracts, it’s great news for South Tyneside, the North East and the UK,” said Metec commercial manager Graeme Crow (pictured). ...

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How To Lose Cred

2021-07-23 15:24 ElectronicsWeekly David Manners

When the first Japanese TVs came to the U.K. the U.K. manufacturers got a shock – they all worked. The U.K. manufacturers accepted a failure rate on the sets they shipped. The public quickly twigged and Japanese TVs became popular. GEC realising, too late, that it could not out-manufacture the Japanese, set up a manufacturing ...

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Brushed servo motors and mini-control boards from EMS

2021-07-23 13:11 ElectronicsWeekly Steve Bush

Berkshire-based Electro Mechanical Systems (EMS) has samples of Nidec Servo’s DMN range brushed electric motors. “Optimised brush design allows intermittent operation over one million cycles and a continuous operating life of 3,000 hours,” according to EMS. “The range achieves this long life cycle while still delivering a high output due to enhanced heat dissipation and ...

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New ML-based tool offers automated chip design flow optimization

2021-07-23 12:15 Embedded.com Nitin Dahad

There’s no debating the fact that chip design is getting more and more complex as customers demand more features and smaller devices and lower power consumption. To meet this demand, engineers are becoming overloaded and need support to keep up with demand and timely product development.

To address this, Cadence Design Systems has introduced a new tool that uses machine learning (ML) to drive the Cadence RTL-to-signoff implementation flow, delivering what it said is up to 10X productivity and 20% PPA (power, performance and area) improvements for implementation. Its new Cerebrus Intelligent Chip Explorer provides more efficient on-site and cloud compute resource management capabilities than traditional human-driven design exploration; and improves PPA and productivity across many nodes and multiple end-applications including consumer, hyperscale computing, 5G communications, automotive and mobile design.

In a briefing with embedded.com, Rod Metcalfe, a product management group director at Cadence, said, “This is the first full flow digital optimization tool using ML. This is important, as design complexity grows, chip design demands more features and intelligence, yet there is a constraint on the number of engineers available to carry out these tasks. We still see designers doing manual flow development and iterate around the loop to meet their design goals: this requires a huge amount of engineering effort and is not scalable. That’s where Cerebrus comes in, using massive compute to improve productivity for design automation.”

Metcalfe highlighted an example where Cerebrus needed just one engineer to converge on an improved design flow within 10 days to automatically improve the PPA of a 5nm mobile CPU (see graphic below).

Cadence Cerebrus productivity example
Using the ML-based tool provides better PPA and full flow productivity. (Source: Cadence)

Another example at a higher level is automated floorplan optimization, as in the graphic below:

Cadence Cerebrus floorplan example
The Cerebrus tool also provides automated floorplan optimization. (Source: Cadence)

The impact of using an ML-based tool like Cerebrus is that design teams have an automated way to reuse historical design knowledge – previously they would have spent excess time on manual re-learning with each new project. Hence Cadence said Cerebrus marks an EDA industry revolution with ML-driven digital chip design where engineering teams have a greater opportunity to provide higher impact in their organizations because they can offload manual processes. As the industry continues to move to advanced nodes and design size and complexity increase, Cerebrus will help designers achieve PPA goals more efficiently.

Early customer endorsements for the tool came from Renesas and Samsung Foundry.

Satoshi Shibatani, director of the digital design technology department in the shared R&D EDA division of Renesas, said, “To efficiently maximize the performance of new products that use emerging process nodes, digital implementation flows used by our engineering team need to be continuously updated. Automated design flow optimization is critical for realizing product development at a much higher throughput. Cerebrus, with its innovative ML capabilities, and the Cadence RTL-to-signoff tools have provided automated flow optimization and floorplan exploration, improving design performance by more than 10%.”

Meanwhile at Samsung Foundry, its vice president for design technology, Sangyun Kim, said, “As we continue to deploy up-to-date process nodes, the efficiency of our design technology co-optimization (DTCO) program is very important. . As part of our long-term partnership with Cadence, Samsung Foundry has used Cerebrus and the Cadence digital implementation flow on multiple applications. We’ve observed more than an 8% power reduction on some of our most critical blocks in just a few days versus many months of manual effort. In addition, we are using Cerebrus for automated floorplan power distribution network sizing, which has resulted in more than 50% better final design timing.

Key features and benefits of Cerebrus are:

  • Reinforcement ML: quickly finds flow solutions human engineers might not naturally try or explore, improving PPA and productivity.
  • ML model reuse: allows design learnings to be automatically applied to future designs, reducing the time to better results.
  • Improved productivity: lets a single engineer optimize the complete RTL-to-GDS flow automatically for many blocks concurrently, allowing full design teams to be more productive.
  • Massively distributed computing: provides scalable on-premises or cloud-based design exploration for faster flow optimization.
  • Easy-to-use interface: powerful user cockpit allows interactive results analytics and run management to gain valuable insights into design metrics.

Cerebrus is part of the broader Cadence digital full flow, working seamlessly with the Genus synthesis solution, Innovus implementation system, Tempus timing signoff solution, Joules RTL power solution, Voltus IC power integrity solution, and Pegasus verification system to provide customers with a fast path to design closure and better predictability.

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Start-up curves the face of CMOS image sensors

2021-07-23 11:58 ElectronicsWeekly Steve Bush

Paris start-up Silina has developed a way to curve hundreds of imaging sensors at the same time, simplifying associated external optics, it said. In nature, most vision systems use curved retinas with the curved retina allowing a single simple lens to provide a wide field-of-view and good image quality from a compact optical system, according to the ...

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Chemistry tames MnSe anodes for Li-ion cells

2021-07-23 11:16 ElectronicsWeekly Steve Bush

Manganese selenide would have promising characteristics as an anode material for lithium ion batteries, if only it didn’t swell almost 160% during charging-discharging cycles, breaking apart the electrode. Now researchers from the Korea Maritime and Ocean University have found a way to embed MnSe in a 3D carbon nanosheet matrix where its expansion can be ...

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Mali-G78 GPU’s Valhall instruction set documentation released after reverse-engineering work

2021-07-23 09:43 CNXSoft Jean-Luc Aufranc (CNXSoft)

Collabora has been working on Panfrost open-source GPU driver for Arm Mali Bifrost and Midgard...


TTElectronics and Radwave partner on EM tracking platform

2021-07-23 07:15 ElectronicsWeekly David Manners

TT Electronics has partnered with Radwave Technologies to help bring a customisable electromagnetic (EM) tracking platform to the surgical navigation market. This technology offers solutions for medical device innovators who are seeking to add new or improved EM capabilities to their medical devices. The complete navigation system can be customised to accurately track a broad spectrum ...

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Farnell releases AIoT Audiobook – Are you Ready for the AIoT Era?

2021-07-23 07:10 ElectronicsWeekly Alun Williams

Farnell has released an audiobook addressing Artificial Intelligence (AI) and the Internet of Things (IoT). It is entitled ‘Are you Ready for the AIoT Era?’ The content is described as an introduction to “Deep Learning, Machine Learning and Artificial Intelligence” with a focus on IoT, addressing the tools and platforms for someone to get started ...

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B-Secur launches ECG/EKG device

2021-07-23 07:00 ElectronicsWeekly David Manners

B-Secur, the Northern Ireland biometric startup, has launched an electrocardiogram (ECG/EKG) device based on TI’s AFE4950 analogue front end for photoplethysmography (PPG) and ECG/EKG sensing. B-Secur says the device will accelerate the design of next-generation consumer wearables. The company claims that the device is the industry’s first product with a fully integrated ECG/EKG and PPG signal chain that ...

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Emerging memories forecast to be a $44bn market in 2031

2021-07-23 07:00 ElectronicsWeekly David Manners

Emerging memory types could become a $44 billion market by 2031 displacing NOR flash, SRAM and DRAM, forecasts a report from Coughlin Associates and Objective Analysis. Memory makers, designers and users of SoCs are already incorporating new NVMs into leading-edge designs and emerging memory types could replace both standalone memory chips and embedded memories within ...

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$5 board eases ATX power supply connection to single board computers

2021-07-23 06:17 CNXSoft Jean-Luc Aufranc (CNXSoft)

Many people have ATX power supplies from older desktop PCs that they may want to...


Tiny Seeeduino XIAO board gets Raspberry Pi RP2040 MCU

2021-07-23 04:47 CNXSoft Jean-Luc Aufranc (CNXSoft)

Seeeduino XIAO is a tiny Arduino Zero compatible board with battery support that was launched...



2021-07-23 02:01 ElectronicsWeekly David Manners

In a masterpiece of self-delusion the EU issued the following statement earlier this week: “The Commission launched the European Alliance on Processors and Semiconductor technologies in July 2021. From smartphones to 5G to the Internet of Things and beyond, processors and semiconductor technologies are crucial for a successful Digital Decade. “The overall objective of the ...

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Modules and dev kits expand upon Qualcomm QCS8250

2021-07-23 00:23 LinuxGizmos Eric Brown

Thundercomm’s “TurboX C865 SOM” and dev kit and eInfochips’ “EIC-QCS8250-210” Mini-ITX run Android 10 on Qualcomm’s QCS8250, an IoT variant of the Snapdragon 865. We also look at the new QCS4290 and Wi-Fi 6E ready QCS6490 SoCs. Last week, we reported on Thundercomm’s TurboX CM2290 and C2290 SOMs, which run Android or Linux on Qualcomm’s […]


Debugging poor performing or unreachable code

2021-07-22 22:01 Embedded.com Aaron Bauch
After completing the first step of making a system work as expected, taking the next steps to optimize your code, improve performance, and eliminate unneeded instructions can be very worthwhile in the long term life of a product.

Developers working with embedded systems have the daily challenge of optimizing resources. The processing power of the MCU’s and MPU’s in embedded systems can be significantly less than that available in desktop, smartphones and servers mostly due to cost factors. Additionally, there is often limited memory available and this means that embedded applications require full control of how the system is behaving in order to fine tune the application to get the best response and performance from the available resources.

Each application is unique and every product has its own technical requirements and specifications. Depending on the application you generally have a maximum time you can spend for processing information and reacting to inputs. This is one accepted definition of real time systems.

Professional compilers are very powerful and can generate optimized code for speed and high performance or for the smallest size. This is however often applied over the entire source code which may not the best solution. An embedded application is often a combination of the application code, middleware and RTOS and the BSP or HAL drivers. It’s a good practice to select different optimization strategies for the different components. The BSP or HAL drivers, generally provided as chip vendor libraries, can probably be optimized for size and the application and RTOS components for speed to get the best result. This might work in some cases however with the resource limitations of embedded systems you might need to fine tune the different modules or functions in order to fit the final output into the available memory.

If you are working with multicore environments, you also have the possibility of distributing the load of the application to the various cores for best performance. Adjustments are likely necessary and this brings us to the need to analyze and measure the performance of the application.

Benchmarks are very common to measure the performance of a specific core and how the generated code affects the efficiency. The most popular benchmarks for embedded hardware are Coremark and Dhrystone that are mainly C code. These contain implementations of different algorithms including list processing (find and sort), matrix manipulation (common matrix operations) and state machine operations (determine if an input stream contains valid numbers).

However, in your own application it might be a bit more complicated to define what is a good enough performance, or if your application is in fact performing poorly. In order to achieve the desired or specified performance, it is necessary to be able to measure actual time consumption of a piece of code in a highly precise manner.

This is made possible by a debugger that supports trace and the capability of logging data accesses.

Reasons for using trace

Trace is a continuously collected sequence of executed instructions for a selected portion of the application. Trace can be collected for every single instruction, for example via the Embedded Trace Macrocell or through discrete event trace via SWO (Serial Wire Output Trace) in case of Arm cores.

Full instruction Trace data is mostly used for locating programming errors that have irregular symptoms and occur sporadically. By using trace, you can inspect the program flow up to a specific state, for instance an application crash, and use the trace data to locate the origin of the problem. However, it can also provide you accurate information about the application’s performance for every routine and line of code executed with cycle level precision. Figure 1 shows a collected sequence of executed machine instructions collected using full instruction Trace.

click for full size image

Figure 1: Collected sequence of executed machine instructions.

The trace information can also be displayed as a call graph in the timeline. This assists developers in analyzing the performance of a live application using the call graph data. Figure 2 shows an example of getting timing information for the selection or functions, with start and end times in a simplified approach displayed as cycle counts and time including the absolute start time, stop time and the difference between the two.

click for full size image

Figure 2: Example of getting timing information from the timeline.

Event graph and data logging with instrumentation

Event messages can be produced when the execution passes specific positions in your application code. To specify the position in your application source code where you want to generate an event message, it is necessary to make use of predefined preprocessor macros available in most Arm development tools supporting the Arm CoreSight features. For example, in IAR Embedded Workbench for Arm, you have the instrumentation macros defined in the arm_itm.h header file and it is required to add the macro calls in your application source code:

void func(void)
// Code whose time you want to measure
// end code
ITM_EVENT32_WITH_PC(2, __get_PSP());

The first line sends an event with the value 25 to channel 1. The second line sends an event with the current value of the stack pointer to channel 2, which means that the debugger can display the stack pointer at a code position of your choice. When these source lines are passed during program execution, events will be generated and visualized, which means that you can further analyze them.

Figure 3 displays the events produced when the execution passes specific positions in your application code. This is extremely powerful when working with an RTOS since it will help you to analyze the task switches that you have during the execution of the application but also very useful when measuring the time specific parts or function of the application take. Notice that if high message rates are generated with multiple message sources you might see data overflow issues. This is because, while the SWO has significant bandwidth, in the range of 10’s of megabits per second, it is not sufficient for high bandwidth operations such as tracing full instruction streams or high speed interrupt and data sampling events.

click for full size image

Figure 3: Events produced with code instrumentation in the timeline.

Reasons for using the profiler

Profiling can help you find the functions in your source code where the most time is spent during execution. You should focus on those functions when optimizing your code. Profiling can help you fine-tune your code on a very detailed level, especially for assembler source code. Profiling can also help you to understand where your compiled C/C++ source code spends its time and perhaps give insight into how to rewrite it for better performance. Figure 4 shows the profiler that follows the program flow and detects function entries and exits:

  • For the InitFib function, Flat Time 231 is the time spent inside the function itself.
  • For the InitFib function, Acc Time 487 is the time spent inside the function itself, including all functions InitFib calls.
  • For the InitFib/GetFib function, Acc Time 256 is the time spent inside GetFib (but only when called from InitFib), including any functions GetFib calls.
  • Further down in the data, you can find the GetFib function separately and see all of its subfunctions (in this case none).

click for full size image

Figure 4: Profiler with function calls.

It is clear that the PutFib function with 3174 cycles run has the highest potential for performance optimizations. A first step might be to split PutFib into smaller modules. Higher speed optimization levels could also help.

Performance Monitoring Unit (PMU)

High-end ARM processors based on Cortex-A and Cortex-R include a Performance Monitor Unit (PMU) which provides useful information about performance, for example event counts and cycle counts. The PMU data is accessed via the CP (Co-processor) register. To access the Co-processors from the code, special instructions MCR (Move from Register to Co-processor) and MRC (Move from Co-processor to Register) are used.

The debugger with a viewer will make it possible to monitor event counters or CPU cycles through the PMU. Figure 5 shows an example of the performance monitoring registers. If you know the CPU clock cycle time, the actual time elapsed can be calculated easily.

Figure 5: Example of the performance monitoring registers.

Notice that to use performance monitoring in your hardware debugger system requires a debug probe that can connect to the PMU through a debug access port (DAP) and the target must have memory-mapped registers. If these requirements are not met, the values of the event counters can only be read when the application execution is stopped.

Unreachable code

Unreachable code is a part of a program’s source code that can never be executed because there is no control flow path to reach the code from anywhere in the rest of the program.

Unreachable code is sometimes referred to as dead code, although dead code can also refer to code that executes but has no effect on the output of a program. Unreachable code is generally considered undesirable for several reasons:

  • Uses program memory unnecessarily
  • Can lead to unnecessary use of the CPU instruction cache
  • Time and effort may be spent testing, maintaining, and documenting code that is never used
  • An optimizing compiler may simply eliminate it making debugging confusing if breakpoints are set in this area

Unreachable code can exist for many reasons, such as:

  • Programming errors in complex conditional branches
  • Incomplete testing of new or changed code
  • Legacy code
  • Unreachable code that a programmer did not want to delete because it was mixed up with accessible code
  • Potentially reachable code that current use cases never need
  • Code only used for debugging

Unreachable code or unused code should not be part of a release build of the application unless there is a strong reason, like code that handles errors or exceptions. Additionally, in order to comply to functional safety standards, you are required to prove full coverage via compressive testing and this might be a stopper.

Code coverage capability helps to verify whether all parts of the application have been executed. It also helps to identify parts of the code that are not reachable.

Reasons for using code coverage

Code coverage functionality is useful when you design your test procedures to verify whether all parts of the code have been executed and therefore at least checked with one execution path. It also helps you identify parts of your code that are not reachable. Figure 6 shows a typical report of the status of the current code coverage analysis. For every program, module, and function, the analysis shows the percentage of code that has been executed since code coverage was turned on up to the point where the application has stopped.

click for full size image

Figure 6: Typical code coverage analysis report.

In addition, all statements that have not been executed are listed.

Only the statement containing the inlined function call is marked as executed. A statement is considered to be executed when all of its instructions have been executed. By default, when a statement has been executed the percentage is increased correspondingly and the window updated.


Taking advantage of comprehensive debugger features can provide more efficient and reliable code.

By eliminating unreachable code, the reliability of a program can be improved. In addition by using code coverage techniques to ensure that all code is executed and tested, including error handling code, can help ensure that a system will behave as expected even when errors occur.

By using tools such as code profilers and performance analyzers to determine the “hot spots” where your application spends most of its time, you can focus your performance optimization efforts on the functions where you can get the best performance gains for your efforts.

This can not only ensure that your system will meet real-time constraints, but it can also be a very effective way to reduce overall system energy requirements.

As a result, it is clear that after the first step of making the system work as expected is completed, taking the next steps to optimize your code, improve performance, and eliminate unneeded instructions can be very worthwhile in the long term life of a product.

Note: Figure images are by IAR Systems unless otherwise noted.

Aaron Bauch is a Senior Field Application Engineer at IAR Systems working with customers in the Eastern United States and Canada. Aaron has worked with embedded systems and software for companies including Intel, Analog Devices and Digital Equipment Corporation. His designs cover a broad range of applications including medical instrumentation, navigation and banking systems. Aaron has also taught a number of college level courses including Embedded System Design as a professor at Southern NH University. Mr. Bauch Holds a Bachelor’s degree in Electrical Engineering from The Cooper Union and a Masters in Electrical Engineering from Columbia University, both in New York, NY.

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QNX 7 BSP available for Toradex Colibri iMX8X SoC modules

2021-07-22 19:41 Embedded.com Nitin Dahad

A new board support package (BSP) from Direct Insight allows the use of QNX 7.0 with the Toradex Colibri iMX8X computer-on-module.

The BSP contains all the basic features required to run the OS on the board. Included are drivers for various interfaces including Ethernet, Watchdog timer, I2C, SPI, USB, SD Card, UART. A display driver is also planned. The BSP is free to download as a demo system, and the source code can be licensed on a per-project basis for a fee. Direct Insight also offers enhancements to the BSP, including additional drivers and production-hardening and testing, as an additional services engagement.

Direct Insight Colibri QNX 7 July 21
The BSP contains all the basic features required to run QNX 7 on the board. Included are drivers for various interfaces including Ethernet, Watchdog timer, I2C, SPI, USB, SD Card, UART. (Source: Direct Insight)

Toradex Colibri iMX8X modules feature the NXP i.MX 8X family of embedded SoCs, including the top-tier i.MX 8QuadXPlus (i.MX 8QXP) which features four Cortex-A35 cores – currently ARM’s most efficient ARM v8 core as the main processor cluster. The SoCs provide full 64-bit ARM v8-A support while maintaining seamless backward compatibility with 32-bit Armv7-A software. The main cores run at up to 1.2 GHz.

The combination of a feature-rich OS like QNX 7 featuring real-time capability and supporting mission-critical systems, with the Arm core processor is suitable for applications such as medical devices, navigation, industrial automation, HMIs (human machine interfaces), avionics, data acquisition, and robotics. David Pashley, Direct Insight’s managing director, said, “The BSP unlocks the full benefits of the QNX OS on the power-efficient Toradex modules. QNX is perfect for real time, safety critical applications, and the BSP created by Direct Insight provides a great starting point for high-availability industrial designs.”

Daniel Lang, CMO at Toradex, added, “We design products for applications that demand high reliability, safety and security, such as medical devices. The QNX offering from Direct Insight further strengthens this positioning and allows our customers to use QNX while lowering the project risk and shortening the time-to-market.”

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Electro-hydraulic actuator animates soft mini-robots

2021-07-22 16:34 ElectronicsWeekly Steve Bush

Electro-hydraulic motion, the mechanism behind the Venus fly trap’s ability to catch insects, could power soft robots, according to the University of Colorado Boulder. “Usually, books about butterflies are static,” said project leader Purnendu. “But could you have a butterfly flap its wings within a book? We’ve shown that it’s possible.” In the Colorado Electro-hydraulic ...

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Fable: Fall Of A Titan

2021-07-22 15:16 ElectronicsWeekly David Manners

141 years ago a company was founded to sell alternators. Five years later it designed a power station in Deptford. In WWII it developed radar systems and made gyro gunsights for Spitfires. It built its first computer in 1951 and sold nine between 1951-7. In 1972 it made a single-chip AM radio and, in 1966, ...

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Aluminium die-cast enclosures are tough, yet easy to machine

2021-07-22 13:14 ElectronicsWeekly Steve Bush

BCL Enclosures has introduced a series of rugged die-cast aluminium alloy enclosures designed to protect electronic instruments. Rated to IP54 against dust ingress and water splashes from any angle, they also provide EMC protection. For easy mounting of PCBs, the side walls have a draft angle of <2°. Casting is to BS1490, LM2M, construction is ...

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MagikEye Developer Kit enables 120 fps 3D sensing on Raspberry Pi

2021-07-22 12:51 CNXSoft Jean-Luc Aufranc (CNXSoft)

MagikEye ILT001 developer kit (DK-ILT001) is a low-latency 3D sensing kit that connects to the...


3d printing at the Olympics

2021-07-22 12:27 ElectronicsWeekly Steve Bush

Zortrax 3D printing equipment has been used to make pistol grips for French Olympic 10m air pistol shooter Celine Goberville – a multiple world champion and already an Olympic silver medallist. They were printed on an M300 Dual 3D printer by French company Athletics 3D, then vapour-smoothed in a Zortrax Apoller – the smoothing step was ...

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Auto chip shortage has bottomed out, says Hyundai exec

2021-07-22 12:19 ElectronicsWeekly David Manners

Hyundai says the chip supply shortage has bottomed out and will improve from now on, reports the Nikkei. “We expect it will get better gradually from the third quarter, although some chips will do so from the fourth quarter,” says a Hyundai exec, “we already ordered chips for 2021 and 2022.” Hyundai says it will ...

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8in TFT display module for industrial and medical

2021-07-22 11:55 ElectronicsWeekly Steve Bush

Review Display Systems (RDS) of Kent has introduced an 8in TFT display module from industrial display manufacturer Tianma. Part of Tianma’s professional (‘P’) series, P0800WVF1MA00 features WVGA (800 x 480 pixels) resolution, 15:9 aspect ratio and -30°C to +80°C operating range. “The Tianma P-series display line-up is designed for use in a wide range of human-machine interface ...

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Osram turns to quantum dots for 90CRI lighting LEDs

2021-07-22 11:23 ElectronicsWeekly Steve Bush

Osram has developed its own emissive quantum dot technology, and is using it in a range of 90CRI lighting LEDs. “‘Osconiq E 2835 CRI90 (QD)’ pushes efficiency values to new heights, even at high colour rendering indices and warm light colours,” according to the company. “The LED meets the requirements of the Single Lighting Regulation ...

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Graphcore IPU integrated into Atos’ ThinkAI offering

2021-07-22 11:21 ElectronicsWeekly David Manners

Atos and Graphcore have signed a partnership to accelerate performance and innovation in AI by integrating Graphcore’s IPU compute systems into Atos’ recently launched ThinkAI offering. This partnership will mutually benefit both parties. Atos’ long-standing position as a European leader in HPC and trusted advisor, provider and integrator of HPC solutions at scale will give ...

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Cortex-M33 MCUs focussed on comms and security

2021-07-22 10:48 ElectronicsWeekly Steve Bush

Renesas is focussing on comms with the RA6M5 group of microcontrollers. “RA6M5 Group MCUs offer numerous communication interface options, including CAN FD, Ethernet MAC with DMA, USB Full Speed and High Speed, and multiple serial interfaces. This gives designers of IoT systems unmatched flexibility in sharing critical data,” according to distributor Anglia, which is stocking ...

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PlasticArm is a functional, non-silicon, flexible Cortex-M0 microcontroller

2021-07-22 10:11 CNXSoft Jean-Luc Aufranc (CNXSoft)

Four years ago, we wrote about PragmatIC’s ultrathin and flexible plastic electronics circuit, with news...


Government announces Innovation Strategy

2021-07-22 07:23 ElectronicsWeekly David Manners

Today, the government is to announce its Innovation Strategy. The main points are: . increase annual public investment on RD to a record £22 billion; . ensure government procurement is proactive and supportive, providing a route to market for innovative new products and services. . consult on how regulation can ensure that the UK is ...

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Worldwide recovery kicks in

2021-07-22 07:22 ElectronicsWeekly David Manners

The recovery in electronics production varies from country to country and the chart below shows the change versus a year ago in electronics production in key Asian countries, reports Semiconductor Intelligence. China was averaging about 10% growth prior to the pandemic. After a sharp drop in early 2020, China recovered to about 10% growth. June ...

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US FTC agrees to pursue right to repair

2021-07-22 07:13 ElectronicsWeekly David Manners

The US FTC has issued a statement saying it is taking steps towards implementing a right to repair policy. ‘First, the Commission urges the public to submit complaints and provide other information to aid in greater enforcement of the Magnuson-Moss Warranty Act and its implementing regulations. While current law does not provide for civil penalties ...

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Tracker Capital gives boost to Accion spacecraft propulsion

2021-07-22 07:10 ElectronicsWeekly Alun Williams

Accion Systems, the spacecraft propulsion specialists spun out of MIT, has announced $42 million in Series C funding led by an affiliate of Tracker Capital Management. The investment both brings Accion Systems’ valuation to $83.5 million and means that the New York-based investor has acquired a majority stake in the company. The investment will support ...

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Foscam SPC WiFi Spotlight Camera Review – Part1: Unboxing and Teardown

2021-07-22 06:44 CNXSoft Jean-Luc Aufranc (CNXSoft)

I’ve been reviewing a few IP cameras with built-in AI features with Vacom Cam, Reolink...


Is TSMC-Sony A Sign Of Things To Come?

2021-07-22 02:31 ElectronicsWeekly David Manners

One wonders if TSMC’s plan to build a 28nm 40k wpm fab in Japan to make image sensors for Sony is a sign of things to come. One normally thinks of a new TSMC fab as being a bleeding edge, industry-leading facility but TSMC has been building trailing edge plants in China for years. This is ...

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Radxa teases larger RK3568 SBC with dual GbE and native SATA

2021-07-21 22:54 LinuxGizmos Eric Brown

Radxa unveiled a “Rock 3 Model B” SBC with the same RK3568 as the Rock 3A but with the addition of WiFi/BT, a second GbE port, native SATA, and M.2 B-key and SIM slots for 4G/5G instead of E-key. A few days after announcing a developer-only launch of its Raspberry Pi style, Rockchip RK3568 based […]


Add-ons supply CAN FD to Raspberry Pi Zero and Pico

2021-07-21 21:25 LinuxGizmos Eric Brown

Copperhill has launched a $71.95 “PiCAN FD Zero” HAT for the Raspberry Pi Zero with CAN FD and a 1A SMPS. There is also a new “CANPico” carrier board that integrates an RPi Pico. Copperhill Technologies has introduced two new CAN FD add-on boards for the Raspberry Pi. The $71.95 PiCAN FD Zero supports the […]


Bio-engineered fibre ‘stronger and tougher than some natural spider silks’

2021-07-21 18:15 ElectronicsWeekly Steve Bush

Researchers at Washington University in St Louis have engineered bacteria to make ‘polymeric amyloid’, which, spun into fibres, achieved average ultimate tensile strength of 980MPa and an average toughness of 161MJ/m3. Lead by professor Fuzhong Zhang, the team was aiming to create a protein that forms ‘β-nanocrystals’, a significant component of natural spider silk. “Spiders have ...

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Display Technology meets SWaP with Litemax night vision system displays

2021-07-21 17:15 ElectronicsWeekly Caroline Hayes

Displays used in defence and avionic installations have their own set of challenging electrical and environmental demands because they are expected to have quiet switching signatures while also conforming to size, weight and power (SWaP) criteria and the ability to operate reliably in harsh environments. Distributor Display Technology has a military portfolio which offers a ...

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Elkhart Lake arrives on Nano-ITX board

2021-07-21 17:10 LinuxGizmos Eric Brown

Portwell’s “Nano-6063” SBC is equipped with Intel’s Atom x6000E with up to 32GB DDR4, triple displays, GbE, 2.5GbE with TSN/TCC, 4x USB 3.1 Gen2, SATA, serial, M.2, mini-PCIe, and -40 to 85°C support. American Portwell has launched an Intel Elkhart Lake based Nano-ITX board, which follows its Apollo Lake powered Nano-6062. This is the first […]


LUNA board enables USB Hacking through Lattice ECP5 FPGA (Crowdfunding)

2021-07-21 16:20 CNXSoft Jean-Luc Aufranc (CNXSoft)

Severa USB hacking/debugging boards were launched in 2020 either based on microcontrollers or FPGA with...


S&P500 CEOs had average earnings of $15.5m last year

2021-07-21 15:22 ElectronicsWeekly David Manners

The average S&P 500 CEO made $15.5 million last year – 299x the pay of the median worker, according to America’s largest labour union, AFL-CIO. The outsize CEO earnings came amidst widespread job losses due to the pandemic. It brings to mind the comment of the 1980s Wall Street CEO at a time when ...

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Honeywell and Cambridge Quantum inch further towards quantum computing

2021-07-21 15:22 ElectronicsWeekly David Manners

Honeywell and Cambridge Quantum have made three advances which suggest that quantum computing is closer than expected. First, researchers at Honeywell Quantum Solutions demonstrated repeated rounds of real-time quantum error correction (QEC). Secondly, the company achieved a quantum volume of 1,024 which was the highest measured on a quantum computer to date. Thirdly, Cambridge Quantum ...

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New Cadence Tensilica DSP supports floating point for optimum PPA

2021-07-21 14:49 Embedded.com Nitin Dahad

Digital signal processors (DSP) play an important role in several real-world applications, including audio and video processing, radar, telecommunication, drive motor control, virtual reality (VR), augmented reality (AR) and, lately, also artificial intelligence (AI) algorithms. Their main purpose is to take the digitized forms of physical analog signals and manipulating them mathematically according to specific algorithms.

Since the beginning, a large volume of DSPs has been designed to support only fixed-point mathematical representation, a reasonable choice since it enables delivery of the accuracy required by most scientific applications. However, floating-point offers a more relevant and accurate way of representing real world data, which are mainly analog signals. Besides, floating point arithmetic representation according to standard IEEE754 is widely used by compilers, development and modeling tools, thus facilitating the integration and porting with DSP code.

“Tensilica has been in the DSP area for a very long time. We have delivered proven products for audio and voice, radar, LiDAR, and computer vision (including AI). This is a completely new family within the Tensilica portfolio, and our first DSPs designed specifically to support floating point arithmetic”, said Ted Chua, director of product management and marketing, Tensilica DSPs at Cadence.

The new Cadence Tensilica FloatingPoint DSP family delivers scalable performance for a broad range of compute-intensive applications featuring an extremely low power consumption. The low-energy DSP IP optimizes power, performance and area (PPA), allowing for an up to 40% area savings for mobile, automotive, consumer and hyperscale computing applications, and provides an easy programming environment for seamless software migration.

“There are applications, such as motor control, where floating point can do a much better job than a fixed-point system, because of smaller code size, or because it runs faster or controls the speed and torque more accurately and more efficiently”, said Chua.

Tensilica FloatingPoint DSP family

The new floating point DSP IP core family, optimized for PPA, extends from small and ultra-low power to very high-performance devices, offering energy-efficient solutions for the most challenging applications, including battery-operated devices, artificial intelligence (AI) and machine learning (ML), motor drive control, sensor fusion, augmented reality (AR) and virtual reality (VR).

Based on the Tensilica Xtensa 32-bit RISC micro-architecture, the new family (figure 1) includes four cores: the Tensilica FloatingPoint KP1 DSP, the Tensilica FloatingPoint KP6 DSP, the Tensilica FloatingPoint KQ7 DSP, and the Tensilica FloatingPoint KQ8 DSP. The new DSPs not only offer a high scalability from 128-bit vector width to 1024-bit vector width but can also be configured to enable only the capabilities required by the specific applications, ranging from energy-efficient solutions for battery-operated devices to high-performance computing (HPC).

Tensilica FloatingPoint DSP family figure 1
Figure 1. The Tensilica FloatingPoint DSP family

The new family DSP cores share a common instruction set architecture (ISA) with existing Tensilica DSPs’ optional vector floating-point unit (VFPU) and feature a scalable vector width from 128-bit SIMD to 1024-bit SIMD on both the Tensilica Xtensa LX and NX platforms. Performance is improved with respect to Tensilica fixed-point DSPs with the VFPU add-on, with a 25% operational throughput increase in fused multiply-add (FMA) operations. Performance can be further enhanced and differentiated using the Tensilica instruction extension (TIE) language, a Cadence proprietary Verilog-like language allows to define custom operations which are automatically integrated and recognized by the Xtensa toolchain. In addition, the FloatingPoint DSPs offer up to 40% area savings compared to the similar class of fixed-point DSPs with VFPUs.

Tensilica FloatingPoint KQ7 and KQ8 block diagram figure 2
Figure 2. Tensilica FloatingPoint KQ7 and KQ8 block diagram.

As shown in Figure 2, the scalable Tensilica FloatingPoint DSP family offers SoC designers design flexibility able to meet their PPA budget envelope. For energy-sensitive applications, the FloatingPoint KP1 DSP offers an ultra-low energy consumption solution, suitable for battery-powered applications. The FloatingPoint KP6 DSP provides an appropriate compromise between high performance and reduced footprint, delivering excellent performance-per-unit area design. For high performance applications, the FloatingPoint KQ7 and KQ8 DSPs offer the maximum family’s vector floating-point operational throughput.

In addition, the common ISA architecture simplifies software portability and migration. The FloatingPoint DSPs provide also support for custom interfaces, such as queues and ports, simplifying the connection and the integration with external hardware blocks or to match the interfaces provided by existing third-party IPs.

Most challenging applications are fast evolving and moving from the cloud to the edge. Computer vision, IoT sensors, self-driving cars, and smart devices are just few examples where artificial intelligence (AI) algorithms are moved at the edge, providing embedded systems with enhanced and autonomous decision-making skills. All these applications need a family of floating-point DSP cores which can address different market needs, reduce time to market, and be optimized for power, performance and silicon area to keep product costs competitive.

“Today, AI inference at the edge is mainly done with fixed point accelerators. Floating point DSP provides an option to execute AI inference or training in the floating-point format, and we all know neural network training is done using floating point representation”, said Chua.

As mentioned previously, configurability is another relevant key factor of the Tensilica FloatingPoint DSP family. Chua commented, “Our Tensilica DSPs are configurable, meaning designers can select only the hardware features they need, without draining unnecessary power.”

Among the most useful options is the scatter-gather capability, which allows the designer to load data from specific memory location and put it in a vector format.

“The floating-point unit inside DSP is a vector machine. For the data that is not stored in consecutive memory locations, the scatter-gather feature allows you load the dispersed data into one vector format, improving the overall performance”, Chua added.

As regards the aspects related to software development, Tensilica FloatingPoint DSPs come with a complete suite of software tools, including a high-perfor­mance C/C++ compiler with automatic vectorization and instruction bundling to support the VLIW pipeline in the DSP, linker, assembler, debugger, profiler, and graphical visualization. A useful tool is the instruction set simulator (ISS), which allows designers to quickly simulate and evaluate performance. When working with large systems or lengthy test vectors, the Tensilica TurboXim simulator option claims to achieve speeds that are 40X to 80X faster than the ISS for efficient software development and functional verification.

Tensilica Xtensa SystemC (XTSC) and C-based Xtensa Modeling Protocol (XTMP) system modeling are available for full-chip simulations. Pin-level XTSC offers co-simulation or SystemC and RTL-level offload accelerator blocks for fast, cycle-accurate simulations. The Tensilica FloatingPoint DSPs support all major back-end EDA flows, including the optimized Eigen library, NatureDSP library, SLAM (simultaneous localization and mapping) library, and math software libraries, making porting and migrating floating-point software much easier.

“With our family of floating-point DSPs, we deliver a set of software tools which is common with all the other software tools for Tensilica DSPs. For any developer who is already familiar with Tensilica software tools, there is really no learning curve, since it is the exact same tool”, said Chua.

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QNX 7 board support package for Toradex Colibri iMX8X

2021-07-21 14:27 ElectronicsWeekly Steve Bush

Direct Insight has created a QNX 7 board support package (BSP) for Toradex’ SODIMM-style Colibri iMX8X embedded computer-on-modules. “The combination of a feature-rich OS with real-time capability and the ARM core processor perfectly suits applications such as medical devices, navigation, industrial automation, HMIs, avionics, POS, data acquisition and robotics,” according to Direct. Colibri iMX8X modules have ...

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Anritsu improves PAM4 analysis in sampling oscilloscope

2021-07-21 13:17 ElectronicsWeekly Steve Bush

Anritsu has upgraded functions for evaluating PAM4 differential electrical signals in its MP2110A sampling oscilloscope. Signal Processing Software Option-098 supports IEEE 802.3-compliant measurement of 50 to 400G PAM4 optical-module electrical interfaces. “Data centres are currently switching to PAM4 optical modules to cope with increase in communications traffic on mobile networks,” said the company. “In line ...

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ReRAMs can be used as PUFs

2021-07-21 12:31 ElectronicsWeekly David Manners

Crossbar, the ReRAM specialist, says its devices can be used as a physical unclonable function (PUF) in order to generate cryptographic keys in secure computing applications. While historically utilized as non-volatile semiconductor memory, CrossBar’s ReRAM technology in now being introduced for use in hardware security applications utilising its ReRAM based cryptographic PUF keys, enabling a ...

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AI camera reference design runs from a battery and includes AI hearing

2021-07-21 12:25 ElectronicsWeekly Steve Bush

Maxim has a unveiled a camera reference design to demonstrate artificial intelligence embedded in space-constrained battery-powered edge devices. MaxRefDes178# “is a cube camera reference design based on the MAX78000 and MAX32666 microcontrollers to help AI at the edge device designers to accelerate their proof-of-concept to the market phase,” according to the company. Measuring 41 x 44 x ...

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Ad-dc chip drives LED lighting at 125W

2021-07-21 10:51 ElectronicsWeekly Steve Bush

Infineon is aiming at LED lighting with a family of single-stage fly-back off-line controller chips for constant voltage outputs. Called ICL88xx, up to 125W can be delivered in primary-side-regulated (right) and opto-coupler secondary-side-regulated configurations. They are optimised as secondary-side regulated constant-voltage output controllers. ICL8800 is the basic variant ICL8810 has added burst-mode operation for <100mW stand-by ...

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